ecn: e-77648?rev. a, new issue l c e e 1 e d e 1 a 2 a a 1 1 -a- b -b- 23 654 AN816 vishay siliconix document number: 71405 15-jan-01 www.vishay.com 1 dual-channel little foot 6-pin sc-70 mosfet copper leadframe version recommended pad pattern and thermal performance michael speed the new dual 6-pin sc-70 package with a copper leadframe enables improved on-resistance values and enhanced thermal performance as compared to the existing 3-pin and 6-pin packages with alloy 42 leadframes. these devices are intended for small to medium load applications where a miniaturized package is required. devices in this package come in a range of on-resistance values, in n-channel and p-channel versions. this technical note discusses pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for the dual-channel version.
figure 1 shows the pin-out description and pin 1 identification for the dual-channel sc-70 device in the 6-pin configuration. both n-and p-channel devices are available in this package ? the drawing example below illustrates the p-channel device. figure 1. sot-363 sc-70 (6-leads) 6 4 1 2 3 5 top view s 1 g 1 d 2 d 1 g 2 s 2
dim min nom max min nom max a 0.90 ? 1.10 0.035 ? 0.043 a 1 ? ? 0.10 ? ? 0.004 a 2 0.80 ? 1.00 0.031 ? 0.039 b 0.15 ? 0.30 0.006 ? 0.012 c 0.10 ? 0.25 0.004 ? 0.010 d 1.80 2.00 2.20 0.071 0.079 0.087 e 1.80 2.10 2.40 0.071 0.063 0.094 e 1 1.15 1.25 1.35 0.045 0.049 0.063 e 0.65bsc 0.026bsc e 1 1.20 1.30 1.40 0.047 0.051 0.055 l 0.10 0.20 0.30 0.004 0.008 0.012 7 nom 7 nom ( datasheet : )
AN816 vishay siliconix www.vishay.com 2 document number: 71405 15-jan-01 figure 2. basic footprints figure 3. sc-70 (6 leads) dual 34 (mil) 21 (mil) 26 (mil) 71 (mil) 0,0 (mil) 654 123 44 (mil) 21 (mil) 654 3 2 1 61 (mil) 26 (mil) 17.5 (mil) 0.0 (mil) 27 (mil) 71 (mil) 105 (mil) 28 (mil) 87 (mil) the basic pad layout and dimensions for the 6-pin sc-70 are shown in figure 2. this pad pattern is sufficient for the low-power applications for which this package is intended. increasing the drain pad pattern (figure 3) yields a reduction in thermal resistance and is a preferred footprint.
the 6-pin sc-70 evaluation board (evb) measures 0.6 in. by 0.5 in. the copper pad traces are the same as in figure 2. the board allows for examination from the outer pins to the 6-pin dip connections, permitting test sockets to be used in evaluation testing. the thermal performance of the dual 6-pin sc-70 has been measured on the evb, comparing both the copper and alloy 42 leadframes. this test was then repeated using the 1-inch 2 pcb with dual-side copper coating. a helpful way of displaying the thermal performance of the 6-pin sc-70 dual copper leadframe is to compare it to the traditional alloy 42 version. front of board sc70-6 back of board sc70-6 sc70?6 dual
AN816 vishay siliconix document number: 71405 15-jan-01 www.vishay.com 3 junction-to-foot thermal resistance (the package performance) thermal performance for the dual sc-70 6-pin package is measured as junction-to-foot thermal resistance, in which the ? foot ? is the drain lead of the device as it connects with the body. the junction-to-foot thermal resistance for this device is typically 80 c/w, with a maximum thermal resistance of approximately 100 c/w. this data compares favorably with another compact, dual-channel package ? the dual tsop-6 ? which features a typical thermal resistance of 75 c/w and a maximum of 90 c/w. power dissipation the typical r ja for the dual-channel 6-pin sc-70 with a copper leadframe is 224 c/w steady-state, compared to 413 c/w for the alloy 42 version. all figures are based on the 1-inch 2 fr4 test board. the following example shows how the thermal resi stance impacts power dissipation for the dual 6-pin sc-70 package at varying ambient temperatures. alloy 42 leadframe room ambient 25 c p d t j(max) t a r ja p d 150 o c 25 o c 413 o c w p 303 mw elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 60 o c 413 o c w p 218 mw copper leadframe room ambient 25 c p d t j(max) t a r ja p d 150 o c 25 o c 224 o c w p 558 mw elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 60 o c 224 o c w p d 402 mw although they are intended for low-power applications, devices in the 6-pin sc-70 dual-channel configuration will handle power dissipation in excess of 0.5 w.
to further aid the comparison of copper and alloy 42 leadframes, figures 5 and 6 illustrate the dual-channel 6-pin sc-70 thermal performance on two different board sizes and pad patterns. the measured steady-state values of r ja for the dual 6-pin sc-70 with varying leadframes are as follows:
alloy 42 copper 1) minimum recommended pad pattern on the evb board (see figure 4). 518 c/w 344 c/w 2) industry standard 1-inch 2 pcb with maximum copper both sides. 413 c/w 224 c/w the results indicate that designers can reduce thermal resistance ( ja) by 34% simply by using the copper leadframe device as opposed to the alloy 42 version. in this example, a 174 c/w reduction was achieved without an increase in board area. if an increase in board size is feasible, a further 120 c/w reduction can be obtained by utilizing a 1-inch 2 . pcb area. the dual copper leadframe versions have the following suf fix: dual: si19xxedh compl.: si15xxedh
AN816 vishay siliconix www.vishay.com 4 document number: 71405 15-jan-01 time (secs) figure 5. dual sc70-6 thermal performance on evb thermal resistance (c/w) 0 1 500 100 200 100 1000 300 10 10 -1 10 -2 10 -3 10 -4 10 -5 alloy 42 400 time (secs) figure 6. dual sc70-6 comparison on 1-inch 2 pcb thermal resistance (c/w) 0 1 500 100 200 100 1000 300 10 10 -1 10 -2 10 -3 10 -4 10 -5 400 copper copper alloy 42
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